SoC Architecture Analysis and Optimization for Performance and Power

Synopsys Platform Architect™ is a SystemC™ standards-based performance and power analysis tool for early SoC architecture exploration and design. Using transaction-level simulation , it reduces design time by predicting and optimizing architecture KPIs. ​

Platform Architect helps optimize hardware-software partitioning, IP selection and configuration, interconnect and memory configuration, and power. ​

Today’s SoC complexity means spreadsheet-based architecture tools are inefficient and run a high risk of re-spins to meet power and performance targets, resulting in higher costs and TTM delay.  With the largest library of architecture models, and fast capture of task and trace-based SW workloads, Platform Architect is the choice to shift-left your architecture design and deliver the right product on schedule.

In addition, Synopsys Platform Architect for Multi-Die Systems accounts for the interdependencies between multiple dies, or chiplets, within multi-die systems.

Key Benefits

Features

  • Largest library of transaction-level performance models
  • Fastest capture of task and trace-based SW workloads​
  • Application specific support (AI, automotive, networking)​
  • System level power analysis based on IEEE-1801 UPF power monitors​
  • Intuitive analysis of tradeoffs and KPIs​
  • Fast design space sweeping and sensitivity analysis​
  • Easy to use UI to dynamically model, simulate, and analyze SoC architecture designs​
  • Command line interface for automated execution of architecture development tasks​
  • IEEE-1666 SystemC standards-based simulation environment
  • Role-based access with Platform Architect Development Kit for collaborative simulation and analysis

 

What's New

What Our Customers Are Saying

Related Architecture Exploration Products

Resources

Synopsys Platform Architect Tool Running on ARC NPX6 NPU Processor IP
Discover how designers can enhance their workflow with the Synopsys Platform Architect and ARC® NP6X NPU Processor IP. This demo shows how the tool helps designers efficiently analyze and optimize their SoCs, demonstrating the stable diffusion of a n
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    Platform Architect Demonstration Running on ARC® NPX NPU Processor IP

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