Performance Analysis for Network-on-Chip Development Using Synopsys Platform Architect

The number of computing and peripheral building blocks in modern System on Chip (SoC) development has been rising significantly during the last three decades and is now often in the 100s. Today, the interconnect between these blocks has become one of the long poles for development and significantly contributes to power consumption and performance. 

Networks-on-Chips (NoCs) have emerged as the key solution for on-chip communication and have seen a rapid rise in protocol complexity for coherent and non-coherent designs. Flows for automated RTL generation from high-level NoC topology descriptions have emerged, and it is critical to enable early architecture optimization to avoid changes late in the design cycle. 

This presentation will outline a flow and methodology that uses early SystemC-based techniques for performance and power optimization during the architecture phase.