Exhibit Booth

Exhibit Dates & Times

• Monday, June 23, 2025: 10:00 AM – 6:00 PM
• Tuesday, June 24, 2025: 10:00 AM – 6:00 PM
• Wednesday, June 25, 2025: 10:00 AM – 4:00 PM

Synopsys Booth #2327

Visit the Synopsys Booth #2327 to network with our experts and check out the following demonstrations:

• Re-engineering EDA with AI

This demo highlights the transformative power of AI in chip design, focusing on breakthrough Generative AI technologies that are enabling chip designers to accelerate development cycles despite increasing design complexity. Assistive technologies boost design productivity by empowering teams with expert-level guidance on tools, workflow execution, and script generation. Creative technologies feature capabilities such as RTL and formal testbench generation, enabling automation of specialized and time-consuming steps in chip design. Agentic AI takes autonomy to the next level, making decisions and executing complex tasks to help designers achieve significantly faster and smarter outcomes. These demos demonstrate how Synopsys’ latest AI technologies can help engineers re-engineer traditional design workflows with AI to boost productivity and accelerate innovation.

• Improving Time-To-Market with Synopsys Cloud FlexEDA

The ever-increasing complexity of chips demands the right set and quantities of EDA applications in different phases of design. Synopsys Cloud was developed to assist in this new era of chip development and enable designers with EDA license elasticity on demand. This demo highlights how Synopsys Cloud unlocks a complete license management solution with FlexEDA licensing. Learn how FlexEDA can improve Time-To-Results drastically with a true Pay-Per-Use model which provides access to virtually unlimited EDA licenses by the minute.

• Expanding Prototyping in the Era of AI with Synopsys HAPS-200

HAPS-200 extends performance and capacity for prototyping of the most complex AI and multi-die designs. Augmenting more than 5,000 HAPS-100 systems in worldwide use and allowing connected setups, HAPS-200 delivers unprecedented value for customers extending their existing investment to next generation prototyping. This demo will show how software developers and system validation engineers find intricate HW/SW bugs and verify interfaces to the real-world at-speed all while being able to prototype a multi-billion gate system. We will also explain how HAPS-200 can be reconfigured – as part of the EP-Ready family – to deliver emulation capability thus optimizing ROI of investments into hardware-assisted verification.

EE Times Chiplet Pavilion Booth #2308

Join Synopsys at the EE Times Chiplet Pavilion at DAC 2025 to hear the latest advancements in multi-die technologies. Hear technical presentations in the areas of power, timing, and physical signoff, AI-driven early architecture exploration, and test for multi-die designs. Stop by our kiosk to network with experts and see demonstrations of our EDA and IP products, optimized to accelerate your multi-die designs.

Synopsys Demonstrations at EE Times Chiplet Pavilion:

• System Analysis and 3D Exploration & Design with Synopsys 3DIC Compiler

This demo features Synopsys' 3DIC Compiler, a unified exploration-to-signoff platform for 2.5D and 3D multi-die designs. The demo highlights how 3DIC Compiler enables floorplan creation, TSV planning, power/ground and signal bump planning, and 3D concurrent placement.

• High Bandwidth Die-to-Die Connectivity with Synopsys UCIe IP

This demo showcases Synopsys’ UCIe IP performing at high bandwidth, allowing more data to travel between dies in a multi-die design. The IP demonstrates high performance with low BER and wide open eyes. Achieving robust and fast die-to-die connectivity is key to realizing successful multi-die designs.