The Synopsys Enhanced Serial Peripheral Interface (eSPI) Controller is compliant to the Intel Base Specification (Rev 1.5) for communication with Embedded Controller (EC), Baseboard Management Controller (BMC), Super-I/O (SIO), flash and debug cards. It replaces the legacy LPC (Low Pin Count) protocol with an SPI-like interface allowing fewer pins (from maximum 13 to 8), higher clock rates (from 33MHz to 66MHz) and lower signalling voltage (from 3.3V to 1.8V).
The Synopsys eSPI Controller IP has an AMBA® AHB bus subordinate interface for programming and data read/write operation. The available features of the Synopsys eSPI controller are completely software programmable via control registers, including SPI transfer mode, eSPI command and response decoding, out of spec command support, serial interface clock rate, CRC protection, and multiple target support.
The Synopsys eSPI controller has the capability to decode incoming commands and drive the transfer on the serial interface accordingly. The IP’s native response decoding frees the application from intervening if the transfer ends prematurely due to target error. On-board status registers provide the user with error indications, operational status, and target malfunction indication. System interrupts can be individually enabled/ disabled to meet user requirements. An internal loop-back capability allows on-chip diagnostics.
Synopsys Enhanced Serial Peripheral Interface (eSPI) Controller IP